H
ARDWARE
R
EFERENCE
G
UIDE
MICRO
-
LINE
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 37
package or a custom FPGA design. Optionally, SDA0 can additionally be connected to the DSP's
I
2
C interface #0, see chapter 7.2.5 for details. When connected, SDA0 has a 10K pull-up resistor.
If the board is configured for I2C #0 usage, then the FPGA may only pull this signal low, according
to the rules of the I
2
C standard.
6.5.4 Connector D
Power GND:
These four pins are the power supply ground pins of the C6713CPU board. Only the power supply
should be connected here. Signal ground should be connected to the ground pins of connector B.
+3.3V:
These two pins provide the power supply for the C6713CPU board. All necessary internal voltages
are generated from this input voltage. Please refer to chapter 7.4 for voltage limits and
recommended operating conditions.
/RESETIN:
This input pin can be used for an external reset button or for a reset output signal from external
hardware. When /RESETIN is driven low, all components of the C6713CPU are reset.
Furthermore, RESETOUT and /RESETOUT are activated so that connected peripheral
components will also get a defined reset signal. The /RESETIN signal does not need to be de-
bounced. The C6713CPU board provides a 10k pull-up resistor on this
input.
/RESETOUT:
This is an active low reset output pin. It allows external hardware to get a defined reset and exactly
be started together with the C6713CPU board. /RESETOUT always becomes active if the
C6713CPU board is reset. There is no difference whether the reset was caused manually by
/RESETIN, power on, a watchdog event, software or a under-voltage condition. In all cases, the
reset condition is asserted by a 200ms (typical) pulse. A 10k pull-up resistor is provided on this
signal for cases, where the C6713CPU is hardware-configured for future use as a slave peripheral
board where /RESETOUT is an input to the
board.
RESETOUT:
This is an inverted /RESETOUT signal, that means an active high reset
signal.
Pins D10 through D16:
These signals are routed to the FPGA. Usage of these signals requires either an ORSYS board
support package or a custom FPGA design. These signals are pulled-up by the FPGA as long as
the FPGA is not loaded.
EXT_INT[5:4]:
These signals are routed to the respective interrupt inputs of the DSP as well as to the FPGA and
have a 10kpull-up resistor. These signals can be used as interrupt inputs even when the FPGA
is not loaded. They can either be driven by an appropriate FPGA design, or by an external source,
but care must be taken that they are never driven by both sources simultaneously. Please note that
the DSP must be configured for falling-edge triggered interrupts as mentioned in chapter 2.5.8.
Pins D19 through D25:
These signals are routed to the FPGA. Usage of these signals requires either an ORSYS board
support package or a custom FPGA design. These signals are pulled-up by the FPGA as long as
the FPGA is not loaded. Further, all of these signals with exception of D24 have a 10k pull-up
resistor. D19 through D21 are intended as additional interrupt inputs, however this usage is not
mandatory.
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